The acronym SPARC stands for Scalable Processor ARChitecture. The SPARC architecture, designed by SUN Microsystems, ensures easy way of using computer systems for all types of users ranging from end users to software developers and system administrators. The SPARC architecture is derived from RISC (Reduced Instuction Set Computer) technology developed at University of California, Berkeley. The SPARC architecture and the system software are openly available to all system developers which are the building blocks for variety of computer systems ranging from laptop computers to supercomputers. The SPARC architecture is scalable across many semiconductor technologies which include CMOS, BiCMOS, ECL and Gallium Arsenide. The combination of semiconductor scalability and architectural scalability permits SPARC system to design various computer systems.
The SPARC CPU has Integer Unit and Floating Unit to perform corresponding calculations. The SPARC based computers have a Memory Management Unit (MMU), a large virtual address cache using 32-bit bus. The MMU architecture can be implemented as a single chip using various semiconductor technologies like CMOS, BiCMOS, ECL and GaAs. The MMU uses three levels of page tables for address translation. The page table entries are cached for translating the address quickly. The MMU has 32-bit virtual address, 36-bit physical address, page of size 4k bytes, and page level protections. The virtual address has the following format.
The lower order 12-bits of virtual address gives the offset within the physical page. For each valid virtual page in main memory there is a corresponding valid entry in page table which contains the physical page number for that virtual page. Virtual page number is replaced by the physical page number by translating the virtual address to the physical address. Mapping a virtual address requires three levels of page tables. The first and second levels contain page table descriptors which point to next level page tables. The third level page table entry points to a physical page.
Each index field provides an offset into the corresponding page table. All page tables are not required every time as virtual address space is thinly populated. If a segment of 256KB, 16MB or 4GB of linear memory is mapped with a single page table entry, the full set of page tables are not required. If for each virtual address translation required all levels of page tables, CPU memory references would become very slow. Hence page table entries are cached in MMU's page descriptor cache or PDC which is often called a TLB or Translation Lookaside Buffer. By Caching the page table entries the access time of a page table is lessened.
