Introduction

In Intel486DX processor memory is divided into 8-bit, 16-bit and 32-bit quantities called byte, word and double word respectively. Words are stored in two consecutive bytes in memory following the little-endian notation as illustrated below.


In little endian notation the lower order byte is stored in lower address and higher order byte is stored in higher order byte. Double words are stored with high order byte at highest byte and low order byte at lowest address. The Intel486DX processor can convert 16 or 32 bit data between the two byte orderings by using two instructions: BSWAP which handles four byte values and XCHG which handles two byte values.

In addition to the above units, the processor also supports two larger units of memory: pages and segments. Segments are variable size blocks of memory whereas pages are all of equal size--usually 4K bytes. Intel486 provides maximum flexibility to the designer by allowing both paging and segmentation.

Address Spaces

Intel486 has three distinct address spaces.

  1. logical or virtual
  2. linear
  3. physical
A logical address consists of two parts: selector and offset. An offset is calculated by using the contents of general purpose registers which are used in diffrent addressing modes. Since the output of a segment register is 14 bits, there are 16K different selectors. Offset is represented by 32 bits (i.e 4 giga bytes). Selector and offset together give 64 tera bytes of logical address which is seen as virtual address space by the programmer.

Paging

Paging divides user's program into multiple pages of same size. At any instant of time, pages which are active, are kept in main memory. This is due to the fact that paging exploits the locality of reference property exhibited by the programs. To learn more about how this set of active pages are chosen see the Yellow Line--Implementation and Performance. The paging mechanism in Intel 80486 processor uses a two level paging scheme.