Performance Issues:

There are 5 parameters that characterize the performance of ATM switching systems. They are 1)Throughput 2)Connection Blocking Probability 3)Cell Loss Probability 4)Switching Delay 5)Jitter on the delay

Throughput:This can be defined as the rate at which the cells depart the switch measured in the number of cell departures per unit time. It mainly depends on the technology and dimensioning of the ATM switch. By choosing a proper topology of the switch, the throughput can be increased.

Connection Blocking probability: Since ATM is connection oriented, there will be a logical connection between the logical inlet and outlet during the connection set up phase. Now the connection blocking probability is defined as the probability that there are not enough resources between inlet and outlet of the switch to assure the quality of all existing as well as new connection.

Cell Loss Probability: In ATM switches, when more cells than a queue in the switch can handle will compete for this queue, cells will be lost. This cell loss probability has to be kept within limits to ensure high reliability of the switch. In Internally Non-Blocking switches, cells can only be lost at their inlets/outlets. There is also possibility that ATM cells may be internally misrouted and they reach erroneously on another logical channel. This is called Cell Insertion Probability.

Switching Delay: This is the time to switch an ATM cell through the switch. The typical values of switching delay range between 10 and 1000Micro Secs. This delay has two parts. 1.Fixed Switching Delay and it is because of internal cell transfer through the hardware. 2.Queueing delay and this is because of the cells queued up in the buffer of the switch to avoid the cell loss.

Jitter on the Delay: This is also called as Cell Delay Variation(CDV) and this is denoted as the probability that the delay of the switch will exceed a certain value. This is called a quantile and for example, a jitter of 100Micro secs at a 10exp-9 quantile means the probability that the delay in the switch is larger than 100Micro secs. is smaller than 10exp-9.


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